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19.5 Register Description
19.5.1 TIMERn_CTRL - Control Register
Offset
0x000
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:28
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
27:24
PRESC
0x0
RW
Prescaler Setting
These bits select the prescaling factor.
Value
0
1
2
3
4
5
6
7
8
9
10
Mode
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
DIV128
DIV256
DIV512
DIV1024
Description
The HFPERCLK is undivided
The HFPERCLK is divided by 2
The HFPERCLK is divided by 4
The HFPERCLK is divided by 8
The HFPERCLK is divided by 16
The HFPERCLK is divided by 32
The HFPERCLK is divided by 64
The HFPERCLK is divided by 128
The HFPERCLK is divided by 256
The HFPERCLK is divided by 512
The HFPERCLK is divided by 1024
23:18
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17:16
CLKSEL
0x0
RW
Clock Source Select
These bits select the clock source for the timer.
Value
0
1
2
Mode
PRESCHFPERCLK
CC1
TIMEROUF
Description
Prescaled HFPERCLK
Compare/Capture Channel 1 Input
Timer is clocked by underflow(down-count) or overflow(up-count) in the lower
numbered neighbor Timer
15:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11:10
FALLA
0x0
RW
Timer Falling Input Edge Action
These bits select the action taken in the counter when a falling edge occurs on the input.
Value
0
1
2
3
Mode
NONE
START
STOP
RELOADSTART
Description
No action
Start counter without reload
Stop counter without reload
Reload and start counter
9:8
RISEA
0x0
RW
Timer Rising Input Edge Action
These bits select the action taken in the counter when a rising edge occurs on the input.
Value
0
1
2
Mode
NONE
START
STOP
Description
No action
Start counter without reload
Stop counter without reload
2011-04-12 - d0001_Rev1.10
261
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